#ISDN adjecent noob question:
The PDH (T1/E1 and stuff) had this problem that each sender had independent clock, which could be slightly faster or slightly slower than the mux, so after some time it may not have sent the next portion of bits when the mux needs to fill its slot in the frame, or it may've sent two.
And SDH claims to solve it by running the whole network on a shared clock.
But how is that clock distributed?
Don't you need an equal-delay clock tree like in an IC?